As semiconductor technologies continuously advance, the gate-last technology has been widely used in the 45 nm process and the 32 nm process, to obtain a desirable threshold voltage and improve the device performance. However, when the Critical Dimension (CD) of devices is further scaled down, the conventional structure of MOS Field-Effect-Transistors can no longer provide satisfactory device performance even if the gate-last technology is employed. As an alternative of the conventional device, the multigate device has drawn a great deal of attention.
A Fin Field-Effect Transistor (FinFET) is a common multigate device. As shown in FIG. 1, a perspective view of the structure of a conventional FinFET, the FinFET comprises: a semiconductor substrate 10, with a fin 101 that protrudes from the semiconductor substrate 10, the fin 101 being generally obtained by etching the semiconductor substrate 10; a dielectric layer 11, covering the surface of the semiconductor substrate 10 and a portion of the sidewalls of the fin 101; and a gate structure 12, formed across the fin 101 and covering the top and the sidewalls of the fin 101, the gate structure 12 comprising a gate dielectric layer (not shown) and a gate electrode (not shown) on the gate dielectric layer. In the FinFET, the portions of the top and sidewalls of the fin 101 that are in contact with the gate structure 12 become the channel region, resulting in multiple gates, and facilitating the increase in drive current and improving device performance. In the prior art, the cross section of the gate structure 12 may have a number of shapes, e.g., Π shape, Ω shape, quadrilateral, or cylinder.
FIG. 2 to FIG. 6 illustrate a conventional method for manufacturing a multigate device.
As shown in FIG. 2, a semiconductor substrate 20 is provided, with a patterned hardmask layer 21 formed on it, the hardmask layer 21 being patterned to define the pattern of the fin. The semiconductor substrate 20 is generally a silicon substrate, and the hardmask layer 21 may be silicon nitride.
As shown in FIG. 3, the semiconductor substrate 20 is etched by using the patterned hardmask layer 21 as a mask, to form a protruding fin 201.
As shown in FIG. 4, a dielectric layer 22 is formed, covering the semiconductor substrate 20, the fin 201 and the patterned hardmask layer 21. The dielectric layer 22 is generally silicon oxide.
As shown in FIG. 5, the surface of the dielectric layer 22 is planarized by chemical mechanical polishing (CMP), and the surface of the dielectric layer 22 and the patterned hardmask layer are removed by etching, such that the top and a portion of the sidewalls of the fin 201 are exposed.
The remanent dielectric layer 22 on the semiconductor substrate 20 can isolate adjacent fins 201. However, the fins 201 are all connected to the semiconductor substrate 20 at their bottoms, causing leakage current between adjacent fins 20. Therefore, ion implantation is needed at the bottom of the fin 201, to form a doped junction for isolation. However, ion implantation based isolation is poor, and the implantation process is hard to control.
FIG. 6 illustrates another method for isolating the fins 201, in which selective lateral oxidation of the remanent dielectric layer 22 is performed, so that the dielectric layer 22 is laterally extended to isolate adjacent fins 201. However, this method has a relatively high processing complexity, requiring a high oxidation temperature, and introduces additional stress in the fin 201, which may affects the performance of the eventual device.
In addition, in the prior art, the fin may be formed on a Silicon-On-Insulator (SOI) substrate. Due to the buried oxide layer of the SOI that is beneath the fins, adjacent fins can be completely isolated. However, manufacturing cost of SOI substrates is relatively high.
For more information regarding the multigate device, please refer to U.S. Pat. No. 6,642,090 and No. 7,449,373.